ICs are widely used today in many different applications such as computers, cellular telephones and consumer electronics. ICs are typically fabricated from disc-shaped wafers of silicon on which large numbers of ICs are formed. One common method of IC fabrication is to deposit various layers of materials on the face of a wafer to form the ICs. The wafers are then cut so that the individual ICs can be separated from one another. The ICs are then packaged and stressed in a burn-in quality assurance test.
Conventional burn-in tests are typically comprised of a pre burn-in test, a burn-in stress, and a post burn-in test. The pre burn-in test, which is a typical post-fabrication test, is performed first by placing a packaged IC in software driven automatic test equipment, such as is fabricated by Helwett-Packard Company of Palo Alto, Calif., Teradyne Inc. of Boston, Mass., and others to test the functionality, i.e. the memory, the digital signal processor, the arithmetic logic, the X and Y registers, and logic states, of the ICs. If the IC passes the pre burn-in test, the IC is then placed in an oven at an elevated temperature for several hours while an accelerated voltage is simultaneously applied to the IC in a predetermined sequence. Thereafter, the IC is again placed in the automatic test equipment for the post burn-in test which is identical to the pre burn-in test. If the IC passes both the pre and post burn-in tests, it can be shipped for use to a customer. If the IC fails either one of the pre or post burn-in tests, then the IC is deemed defective and is discarded.
As part of the aforementioned pre and post burn-in tests of the IC, an I.sub.ddq measurement is taken at a single predetermined voltage. FIG. 1 shows a plot of I.sub.ddq versus voltage for conventional burn-in testing of packaged ICs in which the I.sub.ddq measurement is made at one voltage. The plot shows a dark rectangle denoting a range of acceptable I.sub.ddq measurement. If the I.sub.ddq measured for a particular IC falls within this range then the IC is deemed to have passed this test. If, however, the I.sub.ddq measured for a particular IC exceeds this range, then the unit is deem to have failed this test and is discarded.
Although conventional burn-in testing is effective in identifying ICs which are likely to fail once they are in actual use, the process suffers from several drawbacks. First, the process takes a long time to perform and uses production capacity that could otherwise be used for fabricating ICs, thereby increasing the cost of the ICs. Second, conventional burn-in stressing typically fails to test ICs at voltages sufficiently high enough to identify those ICs having defects such as filament shorts and/or leaks between analog and digital blocks. In fact, conventional burn-in stressing cannot be performed at the voltages required to detect such defects because simultaneously subjecting an IC to the combination of the high temperatures at which the burn-in is performed and the high voltages required to detect such defects will irreparably damage the functionality of the ICs.
Accordingly, there exists a need for a method for quality and reliability assurance testing of fabricated ICs which overcomes the foregoing drawbacks. It is therefore an object of the present invention to provide a method for testing packaged ICs that is performed much more quickly and thus less expensively than conventional burn-in testing, and that also enables ICs having physical defects such as filament shorts and/or leaks to be identified and discarded.